Browse Registers In Our Database

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Registers in Raspberry Pi /RP2350 /DMA

  1. CH0_AL1_CTRL
  2. CH0_AL1_READ_ADDR
  3. CH0_AL1_TRANS_COUNT_TRIG
  4. CH0_AL1_WRITE_ADDR
  5. CH0_AL2_CTRL
  6. CH0_AL2_READ_ADDR
  7. CH0_AL2_TRANS_COUNT
  8. CH0_AL2_WRITE_ADDR_TRIG
  9. CH0_AL3_CTRL
  10. CH0_AL3_READ_ADDR_TRIG
  11. CH0_AL3_TRANS_COUNT
  12. CH0_AL3_WRITE_ADDR
  13. CH0_CTRL_TRIG
  14. CH0_DBG_CTDREQ
  15. CH0_DBG_TCR
  16. CH0_READ_ADDR
  17. CH0_TRANS_COUNT
  18. CH0_WRITE_ADDR
  19. CH10_AL1_CTRL
  20. CH10_AL1_READ_ADDR
  21. CH10_AL1_TRANS_COUNT_TRIG
  22. CH10_AL1_WRITE_ADDR
  23. CH10_AL2_CTRL
  24. CH10_AL2_READ_ADDR
  25. CH10_AL2_TRANS_COUNT
  26. CH10_AL2_WRITE_ADDR_TRIG
  27. CH10_AL3_CTRL
  28. CH10_AL3_READ_ADDR_TRIG
  29. CH10_AL3_TRANS_COUNT
  30. CH10_AL3_WRITE_ADDR
  31. CH10_CTRL_TRIG
  32. CH10_DBG_CTDREQ
  33. CH10_DBG_TCR
  34. CH10_READ_ADDR
  35. CH10_TRANS_COUNT
  36. CH10_WRITE_ADDR
  37. CH11_AL1_CTRL
  38. CH11_AL1_READ_ADDR
  39. CH11_AL1_TRANS_COUNT_TRIG
  40. CH11_AL1_WRITE_ADDR
  41. CH11_AL2_CTRL
  42. CH11_AL2_READ_ADDR
  43. CH11_AL2_TRANS_COUNT
  44. CH11_AL2_WRITE_ADDR_TRIG
  45. CH11_AL3_CTRL
  46. CH11_AL3_READ_ADDR_TRIG
  47. CH11_AL3_TRANS_COUNT
  48. CH11_AL3_WRITE_ADDR
  49. CH11_CTRL_TRIG
  50. CH11_DBG_CTDREQ
  51. CH11_DBG_TCR
  52. CH11_READ_ADDR
  53. CH11_TRANS_COUNT
  54. CH11_WRITE_ADDR
  55. CH12_AL1_CTRL
  56. CH12_AL1_READ_ADDR
  57. CH12_AL1_TRANS_COUNT_TRIG
  58. CH12_AL1_WRITE_ADDR
  59. CH12_AL2_CTRL
  60. CH12_AL2_READ_ADDR
  61. CH12_AL2_TRANS_COUNT
  62. CH12_AL2_WRITE_ADDR_TRIG
  63. CH12_AL3_CTRL
  64. CH12_AL3_READ_ADDR_TRIG
  65. CH12_AL3_TRANS_COUNT
  66. CH12_AL3_WRITE_ADDR
  67. CH12_CTRL_TRIG
  68. CH12_DBG_CTDREQ
  69. CH12_DBG_TCR
  70. CH12_READ_ADDR
  71. CH12_TRANS_COUNT
  72. CH12_WRITE_ADDR
  73. CH13_AL1_CTRL
  74. CH13_AL1_READ_ADDR
  75. CH13_AL1_TRANS_COUNT_TRIG
  76. CH13_AL1_WRITE_ADDR
  77. CH13_AL2_CTRL
  78. CH13_AL2_READ_ADDR
  79. CH13_AL2_TRANS_COUNT
  80. CH13_AL2_WRITE_ADDR_TRIG
  81. CH13_AL3_CTRL
  82. CH13_AL3_READ_ADDR_TRIG
  83. CH13_AL3_TRANS_COUNT
  84. CH13_AL3_WRITE_ADDR
  85. CH13_CTRL_TRIG
  86. CH13_DBG_CTDREQ
  87. CH13_DBG_TCR
  88. CH13_READ_ADDR
  89. CH13_TRANS_COUNT
  90. CH13_WRITE_ADDR
  91. CH14_AL1_CTRL
  92. CH14_AL1_READ_ADDR
  93. CH14_AL1_TRANS_COUNT_TRIG
  94. CH14_AL1_WRITE_ADDR
  95. CH14_AL2_CTRL
  96. CH14_AL2_READ_ADDR
  97. CH14_AL2_TRANS_COUNT
  98. CH14_AL2_WRITE_ADDR_TRIG
  99. CH14_AL3_CTRL
  100. CH14_AL3_READ_ADDR_TRIG
  101. CH14_AL3_TRANS_COUNT
  102. CH14_AL3_WRITE_ADDR
  103. CH14_CTRL_TRIG
  104. CH14_DBG_CTDREQ
  105. CH14_DBG_TCR
  106. CH14_READ_ADDR
  107. CH14_TRANS_COUNT
  108. CH14_WRITE_ADDR
  109. CH15_AL1_CTRL
  110. CH15_AL1_READ_ADDR
  111. CH15_AL1_TRANS_COUNT_TRIG
  112. CH15_AL1_WRITE_ADDR
  113. CH15_AL2_CTRL
  114. CH15_AL2_READ_ADDR
  115. CH15_AL2_TRANS_COUNT
  116. CH15_AL2_WRITE_ADDR_TRIG
  117. CH15_AL3_CTRL
  118. CH15_AL3_READ_ADDR_TRIG
  119. CH15_AL3_TRANS_COUNT
  120. CH15_AL3_WRITE_ADDR
  121. CH15_CTRL_TRIG
  122. CH15_DBG_CTDREQ
  123. CH15_DBG_TCR
  124. CH15_READ_ADDR
  125. CH15_TRANS_COUNT
  126. CH15_WRITE_ADDR
  127. CH1_AL1_CTRL
  128. CH1_AL1_READ_ADDR
  129. CH1_AL1_TRANS_COUNT_TRIG
  130. CH1_AL1_WRITE_ADDR
  131. CH1_AL2_CTRL
  132. CH1_AL2_READ_ADDR
  133. CH1_AL2_TRANS_COUNT
  134. CH1_AL2_WRITE_ADDR_TRIG
  135. CH1_AL3_CTRL
  136. CH1_AL3_READ_ADDR_TRIG
  137. CH1_AL3_TRANS_COUNT
  138. CH1_AL3_WRITE_ADDR
  139. CH1_CTRL_TRIG
  140. CH1_DBG_CTDREQ
  141. CH1_DBG_TCR
  142. CH1_READ_ADDR
  143. CH1_TRANS_COUNT
  144. CH1_WRITE_ADDR
  145. CH2_AL1_CTRL
  146. CH2_AL1_READ_ADDR
  147. CH2_AL1_TRANS_COUNT_TRIG
  148. CH2_AL1_WRITE_ADDR
  149. CH2_AL2_CTRL
  150. CH2_AL2_READ_ADDR
  151. CH2_AL2_TRANS_COUNT
  152. CH2_AL2_WRITE_ADDR_TRIG
  153. CH2_AL3_CTRL
  154. CH2_AL3_READ_ADDR_TRIG
  155. CH2_AL3_TRANS_COUNT
  156. CH2_AL3_WRITE_ADDR
  157. CH2_CTRL_TRIG
  158. CH2_DBG_CTDREQ
  159. CH2_DBG_TCR
  160. CH2_READ_ADDR
  161. CH2_TRANS_COUNT
  162. CH2_WRITE_ADDR
  163. CH3_AL1_CTRL
  164. CH3_AL1_READ_ADDR
  165. CH3_AL1_TRANS_COUNT_TRIG
  166. CH3_AL1_WRITE_ADDR
  167. CH3_AL2_CTRL
  168. CH3_AL2_READ_ADDR
  169. CH3_AL2_TRANS_COUNT
  170. CH3_AL2_WRITE_ADDR_TRIG
  171. CH3_AL3_CTRL
  172. CH3_AL3_READ_ADDR_TRIG
  173. CH3_AL3_TRANS_COUNT
  174. CH3_AL3_WRITE_ADDR
  175. CH3_CTRL_TRIG
  176. CH3_DBG_CTDREQ
  177. CH3_DBG_TCR
  178. CH3_READ_ADDR
  179. CH3_TRANS_COUNT
  180. CH3_WRITE_ADDR
  181. CH4_AL1_CTRL
  182. CH4_AL1_READ_ADDR
  183. CH4_AL1_TRANS_COUNT_TRIG
  184. CH4_AL1_WRITE_ADDR
  185. CH4_AL2_CTRL
  186. CH4_AL2_READ_ADDR
  187. CH4_AL2_TRANS_COUNT
  188. CH4_AL2_WRITE_ADDR_TRIG
  189. CH4_AL3_CTRL
  190. CH4_AL3_READ_ADDR_TRIG
  191. CH4_AL3_TRANS_COUNT
  192. CH4_AL3_WRITE_ADDR
  193. CH4_CTRL_TRIG
  194. CH4_DBG_CTDREQ
  195. CH4_DBG_TCR
  196. CH4_READ_ADDR
  197. CH4_TRANS_COUNT
  198. CH4_WRITE_ADDR
  199. CH5_AL1_CTRL
  200. CH5_AL1_READ_ADDR
  201. CH5_AL1_TRANS_COUNT_TRIG
  202. CH5_AL1_WRITE_ADDR
  203. CH5_AL2_CTRL
  204. CH5_AL2_READ_ADDR
  205. CH5_AL2_TRANS_COUNT
  206. CH5_AL2_WRITE_ADDR_TRIG
  207. CH5_AL3_CTRL
  208. CH5_AL3_READ_ADDR_TRIG
  209. CH5_AL3_TRANS_COUNT
  210. CH5_AL3_WRITE_ADDR
  211. CH5_CTRL_TRIG
  212. CH5_DBG_CTDREQ
  213. CH5_DBG_TCR
  214. CH5_READ_ADDR
  215. CH5_TRANS_COUNT
  216. CH5_WRITE_ADDR
  217. CH6_AL1_CTRL
  218. CH6_AL1_READ_ADDR
  219. CH6_AL1_TRANS_COUNT_TRIG
  220. CH6_AL1_WRITE_ADDR
  221. CH6_AL2_CTRL
  222. CH6_AL2_READ_ADDR
  223. CH6_AL2_TRANS_COUNT
  224. CH6_AL2_WRITE_ADDR_TRIG
  225. CH6_AL3_CTRL
  226. CH6_AL3_READ_ADDR_TRIG
  227. CH6_AL3_TRANS_COUNT
  228. CH6_AL3_WRITE_ADDR
  229. CH6_CTRL_TRIG
  230. CH6_DBG_CTDREQ
  231. CH6_DBG_TCR
  232. CH6_READ_ADDR
  233. CH6_TRANS_COUNT
  234. CH6_WRITE_ADDR
  235. CH7_AL1_CTRL
  236. CH7_AL1_READ_ADDR
  237. CH7_AL1_TRANS_COUNT_TRIG
  238. CH7_AL1_WRITE_ADDR
  239. CH7_AL2_CTRL
  240. CH7_AL2_READ_ADDR
  241. CH7_AL2_TRANS_COUNT
  242. CH7_AL2_WRITE_ADDR_TRIG
  243. CH7_AL3_CTRL
  244. CH7_AL3_READ_ADDR_TRIG
  245. CH7_AL3_TRANS_COUNT
  246. CH7_AL3_WRITE_ADDR
  247. CH7_CTRL_TRIG
  248. CH7_DBG_CTDREQ
  249. CH7_DBG_TCR
  250. CH7_READ_ADDR
  251. CH7_TRANS_COUNT
  252. CH7_WRITE_ADDR
  253. CH8_AL1_CTRL
  254. CH8_AL1_READ_ADDR
  255. CH8_AL1_TRANS_COUNT_TRIG
  256. CH8_AL1_WRITE_ADDR
  257. CH8_AL2_CTRL
  258. CH8_AL2_READ_ADDR
  259. CH8_AL2_TRANS_COUNT
  260. CH8_AL2_WRITE_ADDR_TRIG
  261. CH8_AL3_CTRL
  262. CH8_AL3_READ_ADDR_TRIG
  263. CH8_AL3_TRANS_COUNT
  264. CH8_AL3_WRITE_ADDR
  265. CH8_CTRL_TRIG
  266. CH8_DBG_CTDREQ
  267. CH8_DBG_TCR
  268. CH8_READ_ADDR
  269. CH8_TRANS_COUNT
  270. CH8_WRITE_ADDR
  271. CH9_AL1_CTRL
  272. CH9_AL1_READ_ADDR
  273. CH9_AL1_TRANS_COUNT_TRIG
  274. CH9_AL1_WRITE_ADDR
  275. CH9_AL2_CTRL
  276. CH9_AL2_READ_ADDR
  277. CH9_AL2_TRANS_COUNT
  278. CH9_AL2_WRITE_ADDR_TRIG
  279. CH9_AL3_CTRL
  280. CH9_AL3_READ_ADDR_TRIG
  281. CH9_AL3_TRANS_COUNT
  282. CH9_AL3_WRITE_ADDR
  283. CH9_CTRL_TRIG
  284. CH9_DBG_CTDREQ
  285. CH9_DBG_TCR
  286. CH9_READ_ADDR
  287. CH9_TRANS_COUNT
  288. CH9_WRITE_ADDR
  289. CHAN_ABORT
  290. FIFO_LEVELS
  291. INTE0
  292. INTE1
  293. INTE2
  294. INTE3
  295. INTF0
  296. INTF1
  297. INTF2
  298. INTF3
  299. INTR
  300. INTR1
  301. INTR2
  302. INTR3
  303. INTS0
  304. INTS1
  305. INTS2
  306. INTS3
  307. MPU_BAR0
  308. MPU_BAR1
  309. MPU_BAR2
  310. MPU_BAR3
  311. MPU_BAR4
  312. MPU_BAR5
  313. MPU_BAR6
  314. MPU_BAR7
  315. MPU_CTRL
  316. MPU_LAR0
  317. MPU_LAR1
  318. MPU_LAR2
  319. MPU_LAR3
  320. MPU_LAR4
  321. MPU_LAR5
  322. MPU_LAR6
  323. MPU_LAR7
  324. MULTI_CHAN_TRIGGER
  325. N_CHANNELS
  326. SECCFG_CH0
  327. SECCFG_CH1
  328. SECCFG_CH10
  329. SECCFG_CH11
  330. SECCFG_CH12
  331. SECCFG_CH13
  332. SECCFG_CH14
  333. SECCFG_CH15
  334. SECCFG_CH2
  335. SECCFG_CH3
  336. SECCFG_CH4
  337. SECCFG_CH5
  338. SECCFG_CH6
  339. SECCFG_CH7
  340. SECCFG_CH8
  341. SECCFG_CH9
  342. SECCFG_IRQ0
  343. SECCFG_IRQ1
  344. SECCFG_IRQ2
  345. SECCFG_IRQ3
  346. SECCFG_MISC
  347. SNIFF_CTRL
  348. SNIFF_DATA
  349. TIMER0
  350. TIMER1
  351. TIMER2
  352. TIMER3